1. Field of the Invention
The present invention relates to a switched-capacitor input circuit and an analog-to-digital converter (ADC) including the same and, for example, a method and circuit for correcting an offset component of an input signal of an ADC and, more particularly, to offset correction of an input signal of a switched-capacitor ADC.
2. Description of the Related Art
As a circuit for removing an offset component of an input signal and extracting significant signal information in an ADC, a circuit having a capacitor for offset correction using a switched-capacitor circuit is known (Japanese Patent Laid-Open No. 2003-060505). This circuit performs offset correction at a desired accuracy using a necessary number of binary weighted capacitors.
However, to increase the offset correction accuracy using the technique described in Japanese Patent Laid-Open No. 2003-060505, capacitors having smaller capacitance values need to be added. To double the accuracy, a capacitor having a capacitance value ½ needs to be added. To quadruple the accuracy, a capacitor having a capacitance value ½ and a capacitor having a capacitance value ¼ need to be added. When the capacitance value is decreased to obtain a higher accuracy, the parasitic capacitances of connected wiring lines, switches, and the like become nonnegligible, leading to difficulty in accurately binary weighting the capacitance ratio. This makes it harder to maintain the offset correction accuracy. Hence, there is actually a limit to adding capacitors with smaller capacitance values.